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april 2010 doc id 9497 rev 8 1/52 1 m41st87y M41ST87W 5.0 v and 3.3/3.0 v secure se rial rtc and nvram supervisor with tamper detection and 128 bytes of clearable nvram features 5.0, 3.3, or 3.0 v operation 400 khz i 2 c bus nvram supervisor to non-volatize external lpsram 2.5 to 5.5 v oscillato r operating voltage automatic switchover and deselect circuitry choice of power-fail deselect voltages ? m41st87y: ths = 1: v pfd 4.63 v; v cc = 4.75 to 5.5 v ths = 0: v pfd 4.37 v; v cc = 4.5 to 5.5 v ? M41ST87W: ths = 1: v pfd 2.9 v; v cc = 3.0 to 3.6 v ths = 0: v pfd 2.63 v; v cc = 2.7 to 3.6 v two independent power-fail comparators (1.25 v reference) counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century 128 bytes of clearable, general purpose nvram programmable alarm and interrupt function (valid even during battery backup mode) programmable watchdog timer unique electronic serial number (8-byte) 32 khz frequency output available upon power- on microprocessor powe r-on reset output battery low flag ultra-low battery supply current of 500 na (typ) security features tamper indication circuits with timestamp and ram clear lpsram clear function (tp clr ) packaging includes a 28-lead, embedded crystal soic and a 20-lead ssop oscillator stop detection 28-pin, (300 mil) sox28 (mx) embedded crystal ssop20 (ss) www.st.com
contents m41st87y, M41ST87W 2/52 doc id 9497 rev 8 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 security features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.1 bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.2 start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.3 stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.4 data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.5 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4 data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5 tamper detection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6 tamper register bits (tamper 1 and tamper 2) . . . . . . . . . . . . . . . . . . . . . 18 2.6.1 tamper enable bits (teb1 and teb2) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6.2 tamper bits (tb1 and tb2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.6.3 tamper interrupt enable bits (tie1 and tie2) . . . . . . . . . . . . . . . . . . . . 19 2.6.4 tamper connect mode bit (tcm1 and tcm2) . . . . . . . . . . . . . . . . . . . . 19 2.6.5 tamper polarity mode bits (tpm1 and tpm2) . . . . . . . . . . . . . . . . . . . . 19 2.6.6 tamper detect sampling (tds1 and tds2) . . . . . . . . . . . . . . . . . . . . . . 22 2.6.7 tamper current high/tamper current low (tchi/tclo1 and tchi/tclo2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.6.8 ram clear (clr1 and clr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.6.9 ram clear external (clr1 ext and clr2 ext ) - available in sox28 package only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.7 tamper detection operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.8 sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.9 internal tamper pull-up/down current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.10 avoiding inadvertent tampers (normally closed configuration) . . . . . . . . . 27 2.11 tamper event time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.0.1 power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
m41st87y, M41ST87W contents doc id 9497 rev 8 3/52 3.1 timekeeper ? registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2 calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.3 setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.4 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.5 square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.6 full-time 32 khz square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.7 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.8 reset inputs (rstin1 & rstin2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.9 power-fail comparators (1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.10 power-fail outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.11 century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.12 output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.13 battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.14 t rec bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.15 electronic serial number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.16 oscillator stop detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.17 initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
list of tables m41st87y, M41ST87W 4/52 doc id 9497 rev 8 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. tamper detection truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4. tamper detection current (normally closed - tcm x = '0') . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 5. tamper detect timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 6. calculated cut-off frequency for typical capaci tance and resistance values. . . . . . . . . . . . 27 table 7. timekeeper ? register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 8. alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 9. square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 10. reset ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 11. century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 12. t rec definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 13. default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 14. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 15. dc and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 16. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 17. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 18. crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 19. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 20. sox28 ? 28-lead plastic small outline, 300 mils, embedded crystal mechanical data . . . . 47 table 21. ssop20 ? 20-lead, shrink, small outline package mechanical data. . . . . . . . . . . . . . . . . . 48 table 22. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 23. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
m41st87y, M41ST87W list of figures doc id 9497 rev 8 5/52 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. 28-pin, 300 mil soic (mx) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. 20-pin, ssop (ss) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 figure 9. slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10. read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11. alternate read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 13. write cycle timing: rtc & external sram control signals. . . . . . . . . . . . . . . . . . . . . . . . 17 figure 14. tamper detect connection options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 15. basic tamper detect options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 16. tamper detect output options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 17. tamper detect sampling options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 18. tamper current options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 19. tamper output timing (with clr1 ext or clr2 ext = '1') - available in sox28 (mx) package only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 20. ram clear hardware hookup (sox28 mx package only). . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 21. low-pass filter implementation for noise immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 22. crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 23. calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 24. alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 25. backup mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 26. rstin1 & rstin2 timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 27. ac testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 28. power down/up mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 29. sox28 ? 28-lead plastic small outline, 300 mils, embedded crystal outline. . . . . . . . . . . . 47 figure 30. ssop20 ? 20-lead, shrink, small outline package outline . . . . . . . . . . . . . . . . . . . . . . . . . 48
description m41st87y, M41ST87W 6/52 doc id 9497 rev 8 1 description the m41st87y/w secure serial rtc and nvram supervisor is a low power 1280-bit, static cmos sram organized as 160 bytes by 8 bi ts. a built-in 32.768 khz oscillator (internal crystal-controlled) and 8 bytes of the sram (see table 7 ) are used for the clock/calendar function and are configured in binary coded decimal (bcd) format. an additional 11 bytes of ram provide calibration, status/control of alarm, watchdog, tamper, and square wave functions. 8 bytes of rom and finally 128 bytes of user ram are also provided. addresses and data are transferred serially via a two line, bidirectional i 2 c interface. the built-in address register is incremented automatically after each write or read data byte. the m41st87y/w has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. the energy needed to sustain the sram and clock operations can be supplied by a small lithium button-cell supply when a power failure occurs. functions available to the user include a non-volatile, time-of-day clock/calendar, alarm interrupts, tamper detection, watchdog timer, and programmable square wave output. other features include a power-on reset as well as two additional debounced inputs (rstin1 and rstin2 ) which can also generate an output reset (rst ). the eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24-hour bcd format. corrections for 28, 29 (leap year), 30 and 31 day months are made automatically. 1.1 security features two fully independent tamper detection inputs allow monitoring of multiple locations within the system. user programmable bits provide both normally open and normally closed switch monitoring. time stamping of the tamper event is automatically provided. there is also an option allowing data stored in either internal memory (128 bytes), and/or external memory to be cleared, protecting sensitive information in the event tampering occurs. by embedding the 32 khz crystal in the sox28 package, the clock is completely isolated from external tampering. an oscillato r fail bit (of) is also provided to ensure correct operation of the oscillator. the m41st87y/w is supplied in a 28-pin, 300 mil soic package (mx) which includes an embedded 32 khz crystal and a 20-pin ssop package (ss) for use with an external crystal. the soic and ssop packages are shipped in plastic anti-static tubes or in tape & reel form. the 300 mil, embedded crystal soic requires only a user-supplied battery to provide non- volatile operation.
m41st87y, M41ST87W description doc id 9497 rev 8 7/52 figure 1. logic diagram 1. open drain output. 2. programmable output (open drain or full-cmo s). defaults to open drain on first power-up. 3. available in sox28 (mx) package only. 4. available in ssop (ss) package only. ai07023 scl v cc m41st87y M41ST87W ex (3) v ss v bat sda rstin1 irq/out (1) sqw/ft (2) wdi (3) rstin2 (3) tp1 in pfi 2 tp2 in pfi 1 e con (3) rst (1) pfo 1 (2) pfo 2 (2) v out f 32k (1) tp clr (3) xo (4) xi (4)
description m41st87y, M41ST87W 8/52 doc id 9497 rev 8 figure 2. 28-pin, 300 mil soic (mx) connections note: no function (nf) and no connect (nc) pins should be tied to v ss . pins 1, 2, 3, and 4 are internally shorted together. figure 3. 20-pin, ssop (ss) connections note: no connect (nc) pin should be tied to v ss . ai07025b 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 28 27 26 25 24 23 1 rstin1 rstin2 pfi 2 nf nc sqw/ft wdi nf nc irq/out f 32k v out tp1 in ex pfi 1 scl tp clr pfo 1 e con v ss v bat tp2 in sda rst nf nf v cc m41st87y M41ST87W pfo 2 ai07025c 8 2 3 4 5 6 7 9 10 14 13 12 11 20 19 18 17 16 15 1 rstin1 x2 sqw/ft pfi 2 irq/out f 32k v out tp1 in pfi 1 scl nc pfo 1 v ss v bat tp2 in sda rst x1 v cc m41st87y M41ST87W pfo 2
m41st87y, M41ST87W description doc id 9497 rev 8 9/52 table 1. signal names xi (1) 1. available in ssop (ss) package only. oscillator input xo (1) oscillator output e con (2) 2. available in sox28 (mx) package only. conditioned chip enable output ex (2) external chip enable irq /out (3) 3. open drain output. interrupt/out output (open drain) pfi 1 power fail input 1 pfi 2 power fail input 2 pfo 1 (4) 4. programmable output (open drain or full-cmos). power fail output 1 pfo 2 (4) power fail output 2 rst (3) reset output (open drain) rstin1 reset 1 input rstin2 (2) reset 2 input scl serial clock input sda serial data input/output sqw/ft (4) square wave output/frequency test wdi (2) watchdog input v cc supply voltage v out voltage output v ss ground f 32k (3) 32 khz square wave output (open drain) tp1 in tamper pin 1 input tp2 in tamper pin 2 input tp clr (2) tamper pin ram clear v bat positive battery pin input nf (5) 5. should be connected to v ss . no function nc (5) no connect
description m41st87y, M41ST87W 10/52 doc id 9497 rev 8 figure 4. block diagram 1. open drain output. 2. programmable output (open drain or full -cmos); if open drain option is selected and if pulled-up to supply other than v cc , this supply must be equal to, or less than v bat when v cc = 0 v (during battery backup mode). 3. available in sox28 (mx) package only. 4. crystal is external on ssop (ss) pack age and internal for the sox28 (mx) package. ai07026 compare v pfd v cc v out compare v so v out v bl bl compare crystal (4) i 2 c interface real time clock calendar 128 bytes user ram 8 bytes rom rtc w/alarm & calibration watchdog square wave tamper sda scl 1.25v pfi 1 pfi 2 pfo 1 (2) pfo 2 (2) rstin1 por sqw/ft (2) rst (1) wdi (3) tpx in wds tie x clr x clrx ext afe ofie irq/out (1) v bat 32khz oscillator tp clr f 32k (1) compare compare rstin2 (3) ex (3) e con (3) (internal) 1.25v (internal) v ss 2 xi xo (3)
m41st87y, M41ST87W description doc id 9497 rev 8 11/52 figure 5. hardware hookup 1. available in sox28 (mx) package only. ai07027 v cc pfo 1 ex (1) scl m41st87y/w wdi (1) rstin1 rstin2 (1) pfi 1 pfi 2 v ss v bat f 32k irq/out sqw/ft rst v out e con (1) sda unregulated voltage 5v regulator v cc v in 3.3v regulator v cc v in tp1 in tp clr tp2 in pushbutton reset for monitoring of additional voltage sources pfo 2 low-power sram v cc e to microprocessor to led display to nmi to int to 32khz r1 r2 r3 r4 (1)
operating modes m41st87y, M41ST87W 12/52 doc id 9497 rev 8 2 operating modes the m41st87y/w clock operates as a slave device on the serial bus. access is obtained by implementing a start condition followed by the correct slave address (d0h). the 160 bytes contained in the device can then be accessed sequentially in the following order: 00h. tenths/hundredths of a second register 01h. seconds register 02h. minutes register 03h. century/hours register 04h. day register 05h. date register 06h. month register 07h. year register 08h. control register 09h. watchdog register 0ah-0eh. alarm registers 0fh. flag register 10h-12h. reserved 13h. square wave 14h. tamper register 1 15h. tamper register 2 16h-1dh. serial number (8 bytes) 1eh-1fh. reserved (2 bytes) 20h-9fh. user ram (128 bytes) the m41st87y/w clock continually monitors v cc for an out-of-tolerance condition. should v cc fall below v pfd , the device terminates an access in progress and resets the device address counter. inputs to the de vice will not be recognized at th is time to prevent erroneous data from being written to the device from a an out-of-tolerance system. when v cc falls below v so , the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conser ve battery life. as system power returns and v cc rises above v so , the battery is disconnected, and the device is switched to external v cc . write protection continues until t rec (min) elapses after v cc reaches v pfd (min). for more information on battery storage life refer to application note an1012.
m41st87y, M41ST87W operating modes doc id 9497 rev 8 13/52 2.1 2-wire bus characteristics the bus is intended for communication between different ics. it consists of two lines: a clock signal (scl) and a bidirectional data signal (sda). the sda line must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line, while the clock lin e is high, will be interpreted as control signals. accordingly, the following bus conditions have been defined: 2.1.1 bus not busy both data and clock lines remain high. 2.1.2 start data transfer a change in the state of the data line, from high to low, while the clock is high, defines the start condition. 2.1.3 stop data transfer a change in the state of the data line, from low to high, while the clock is high, defines the stop condition. 2.1.4 data valid the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start co ndition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowledges with a ninth bit. by definition a device that gives out a message is called ?transmitter,? the receiving device that gets the message is called ?receiver.? th e device that controls the message is called ?master.? the devices that are controlled by the master are called ?slaves.? 2.1.5 acknowledge each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this
operating modes m41st87y, M41ST87W 14/52 doc id 9497 rev 8 case the transmitter must leave the data line high to enable the master to generate the stop condition. figure 6. serial bus data transfer sequence figure 7. acknowledgement sequence figure 8. bus timing requirements sequence ai00587 data clock data line stable data valid start condition change of data allowed stop condition ai00601 data output by receiver data output by transmitter scl from master start clock pulse for acknowledgement 12 89 msb lsb ai00589 sda p t su:sto t su:sta t hd:sta sr scl t su:dat t f t hd:dat t r t high t low t hd:sta t buf s p
m41st87y, M41ST87W operating modes doc id 9497 rev 8 15/52 table 2. ac characteristics 2.2 read mode in this mode the master reads the m41st87y/w slave after setting the slave address (see figure 9 on page 16 ). following the write mode control bit (r/w =0) and the acknowledge bit, the word address 'an' is written to the on-chip address pointer. next the start condition and slave address are repeated followed by the read mode control bit (r/w =1). at this point the master transmitter becomes the master receiver. the data byte which was addressed will be tran smitted and the master receiver will send an acknowledge bit to the slave transmitter. the address pointer is only incremented on reception of an acknowledge cl ock. the m41st87y/w slave transmitter will now place the data byte at address an+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to an+2. this cycle of reading consecutive addresses will continue until the mast er receiver sends a stop condition to the slave transmitter (see figure 10 on page 16 ). the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume ei ther due to a stop condition or when the pointer increments to a non-clock or ram address. note: this is true both in read mode and write mode. an alternate read mode may also be implemented whereby the master reads the m41st87y/w slave without first writing to the (volatile) address pointer. the first address that is read is the last one stored in the pointer (see figure 11 on page 16 ). symbol parameter (1) 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 4.5 to 5.5 v or 2.7 to 3.6 v (except where noted). min max unit f scl scl clock frequency 0 400 khz t buf time the bus must be free before a new transmission can start 1.3 s t expd (2) 2. available in sox28 (mx) package only. ex to e con propagation delay m41st87y 10 ns M41ST87W 15 ns t f sda and scl fall time 300 ns t hd:dat (3) 3. transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of scl. data hold time 0 s t hd:sta start condition hold time (after this period the first clock pulse is generated) 600 ns t high clock high period 600 ns t low clock low period 1.3 s t r sda and scl rise time 300 ns t su:dat data setup time 100 ns t su:sta start condition setup time (only relevant for a repeated start condition) 600 ns t su:sto stop condition setup time 600 ns
operating modes m41st87y, M41ST87W 16/52 doc id 9497 rev 8 figure 9. slave address location figure 10. read mode sequence figure 11. alternate read mode sequence ai00602 r/w slave address start a 01000 11 msb lsb ai00899 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address s start r/w slave address ack ai00895 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x slave address
m41st87y, M41ST87W operating modes doc id 9497 rev 8 17/52 2.3 write mode in this mode the master transmitter transmits to the m41st87y/w slave receiver. bus protocol is shown in figure 12 . following the start condition and slave address, a logic '0' (r/w = 0) is placed on the bus and indicates to the addressed device that word address an will follow and is to be written to the on-chip add ress pointer. th e data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the ram on the reception of an acknowledge clock. the m41st87y/w slave receiver will send an acknowl edge clock to the master transmitter after it has received the slave address (see figure 9 on page 16 ) and again after it has received the word address and each data byte. figure 12. write mode sequence figure 13. write cycle timing: rtc & external sram control signals 1. available in sox28 (mx) package only. 2.4 data retention mode with valid v cc applied, the m41st87y/w can be accessed as described above with read or write cycles. should the supply voltag e decay, the m41st87y/w will automatically deselect, write protecting itself (and any external sram) when v cc falls between v pfd (max) and v pfd (min) (see figure 28 on page 46 , table 19 on page 46 ). this is accomplished by internally inhibiting access to the clock registers. at this time, the reset pin (rst ) is driven active and will remain active until v cc returns to nominal levels. external ram access is inhibited in a similar manner by forcing e con to a high level. this level is within 0.2 volts of the v bat . e con will remain at this level as long as v cc remains at an out- of-tolerance condition. when v cc falls below the battery backup switchover voltage (v so ), ai00591 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address ai03663 ex (1) e con (1) t expd t expd
operating modes m41st87y, M41ST87W 18/52 doc id 9497 rev 8 power input is switched from the v cc pin to the battery, and the clock registers and external sram are maintained from the attached battery supply. all signal outputs become high impedance. the v out pin is capable of supplying 100a of current to the attached memory with less than 0.3 volts drop under this condition. on power up, when v cc returns to a nominal value, write protection continues for t rec by inhibiting e con . the rst signal also remains active during this time (see figure 28 on page 46 ). note: most low power srams on the market today can be used with the m41st87y/w rtc supervisor. there are, however some criteria which should be used in making the final choice of an sram to use. the sram must be designed in a way where the chip enable input disables all other inputs to the sram. this allows inputs to the m41st87y/w and srams to be ?don ?t care? once v cc falls below v pfd (min). the sram should also guarantee data retention down to v cc = 2.0 volts. the chip enable access time must be sufficient to meet the system needs with the chip enable output propagation delays included. if the sram includes a second chip enable pin (e2), this pin should be tied to v out . if data retention lifetime is a cr itical parameter for the system, it is important to review the data retention current specifications for the particular srams being evaluated. most srams specify a data retention current at 3.0 volts. manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). the system leve l requirements will dete rmine the choice of which value to use. the data retention current value of the srams can then be added to the i bat value of the m41st87y/w to determine the total current requirements for data retention. the available battery capacity for the battery of your choice can then be divided by this current to determine the amount of data retention available. for a further more detailed review of lifetime calculations, please see application note an1012. 2.5 tamper detection circuit the m41st87y/w provides two independent input pins, the tamper pin 1 input (tp1 in ) and tamper pin 2 input (tp2 in ), which can be used to monitor two separate signals which can result in the associated setting of the tamper bits (tb1 and/or tb2, in flag register 0fh) if the tamper enable bits (teb1 and/or teb2) are enabled, for the respective tamper 1 or tamper 2 channels. the tp1 in pin or tp2 in pin may be set to indicate a tamper event has occurred by either 1) closing a switch to ground or v out (normally open), or by 2) opening a switch that was previously closed to ground or v out (normally closed), depending on the state of the tcm x bits and the tpm x bits in the tamper register (14h and/or 15h). 2.6 tamper register bits (tamper 1 and tamper 2) 2.6.1 tamper enable bits (teb1 and teb2) when set to a logic '1,' this bit will enable the tamp er detection circuit. this bit must be set to '0' in order to clear the associated tamper bits (tb x , in 0fh). note: 1 teb x should be cleared then set again whenever the tamper detect condition is modified. 2 when servicing a tamper interrupt, the teb x bits must be cleared to clear the tb x bits, then set to 1 to again enable the tamper detect circuits.
m41st87y, M41ST87W operating modes doc id 9497 rev 8 19/52 2.6.2 tamper bits (tb1 and tb2) if the teb x bit is set, and a tamper condition occurs, the tb x bit will be set to '1.' this bit is ?read-only? and is reset only by setting the teb x bit to '0.' these bits are located in the flags register 0fh. 2.6.3 tamper interrupt enable bits (tie1 and tie2) if this bit is set to a logic '1,' the irq /out pin will be activated w hen a tamper event occurs. this function is also valid in battery backup if the abe bit (alarm in battery backup) is also set to '1' (see figure 15 on page 21 ). note: in order to avoid an inad vertent activation of the irq /out pin due to a prior tamper event, the flag register (0fh) should be read prior to clearing and again setting the teb x bit. 2.6.4 tamper connect m ode bit (tcm1 and tcm2) this bit indicates whether the position of the external switch selected by the user is in the normally open (tcm x = '1') or normally closed (tcm x = '0') position (see figure 14 on page 20 and figure 16 on page 21 ). 2.6.5 tamper polarity mode bits (tpm1 and tpm2) the state of this bit indicates whether t he tamper pin input will be taken high (to v out if tpm x = '1') or low (to v ss if tpm x = '0') to trigger a tamper event (see figure 14 on page 20 and figure 16 on page 21 ).
operating modes m41st87y, M41ST87W 20/52 doc id 9497 rev 8 figure 14. tamper detect connection options note: these options are summarized in table 3 . 1. if the clrx ext bit is set, a second tamper to v out (tpm2 = '1') during t clr will not be detected. 2. if the clrx ext bit is set, a second tamper to v out (tpm2 = '1') will trigger automatically. 3. optional external resistor to v cc allows the user to bypass sampling when power is ?on.? table 3. tamper detection truth table option mode tcm x tpm x i normally open/tamper to gnd (1) 1. no battery current drawn during battery backup. 10 ii normally open/tamper to v out (1) 11 iii normally closed/tamper to gnd 0 0 iv normally closed/tamper to v out 01 ai07075 tp in tamper hi (tpm x = 1) tamper lo (tpm x = 0) v out (1) tp in normally closed (tcm x = 0) normally open (tcm x = 1) i. iv. ii. iii. tp in v out (2) tchi/tclo = 0 tchi/tclo = 1 tchi/tclo = 0 tchi/tclo = 1 v out (int) v cc (3)
m41st87y, M41ST87W operating modes doc id 9497 rev 8 21/52 figure 15. basic tamper detect options 1. available in sox28 (mx) package only. figure 16. tamper detect output options 1. available in sox28 (mx) package only. ai07818 tamper lo, normally open tamper hi, normally closed user configuration tcm x , tpm x irq - interrupt the processor on tamper tp clr - clear external ram on tamper (1) clr - clear internal ram on tamper time stamp tamper event clrx ext tie x clrx tamper hi, normally open tamper lo, normally closed triggering event tamper event output tcm x , tpm x = 1,1 tcm x , tpm x = 0,0 tcm x , tpm x = 1,0 tcm x , tpm x = 0,1 v cc (v out ) v cc (v out ) v cc (v out ) ai07821 irq - interrupt the processor on tamper user configuration tp clr - clear external ram on tamper (1) reset out clr - clear 128 bytes internal ram on tamper time stamp tamper event (to rtc) clr1 ext tie 1 clr1 clr2 ext tie 2 clr2 (other reset sources) teb2 tp2 teb1 tp1
operating modes m41st87y, M41ST87W 22/52 doc id 9497 rev 8 2.6.6 tamper detect sampling (tds1 and tds2) this bit selects between a 1hz sampling rate or constant monitoring of the tamper input pin(s) to detect a tamper event when the normally closed switch mode is selected. this allows the user to reduce the current drain when the teb x bit is enabled while the device is in battery backup (see table 4 on page 23 and figure 17 on page 23 ). sampling is disabled if the tcm x bit is set to logic '1' (normally open). in this case the state of the tds x bit is a ?don?t care.? note: the crystal oscillator must be ?on? for sampling to function . if the oscillator is stopped, the tamper detect circuit will reve rt to continuous monitoring. 2.6.7 tamper current high/t amper current low (tchi/tclo 1 and tchi/tclo 2) this bit selects the strength of the internal pull-up or pull-down used during the sampling of the normally closed condition. the state of the tchi/tclo x bit is a ?don?t care? for normally open (tcm x = '1') mode (see figure 18 on page 24 ). 2.6.8 ram clear (clr1 and clr2) when either clr1 or clr2 and the teb x bit are set to a logic '1,' the internal 128 bytes of user ram (see figure 15 on page 21 ) will be cleared to all zeros in the event of a tamper condition. furthermore, the 128 bytes of user ram will be deselected (inaccessible) until the corresponding teb x bit is reset to '0.' any data read during this time will be invalid. (ie. the cleared ram values cannot be accessed.) 2.6.9 ram clear external (clr1 ext and clr2 ext ) - available in sox28 package only when either clr1 ext or clr2 ext is set to a logic '1' and the teb x bit is also set to logic '1,' the tp clr signal will be asserted for clearing external ram, and the rst output asserted upon detection of a tamper event (see figure 15 on page 21 and figure 20 on page 25 ). note: the reset output resulting from a tamper ev ent will be the same as a reset resulting from a power-down condition, a watchdog time-out, or a manual reset (rstin1 or rstin2 ); the rst output will be asserted for t rec seconds. this is accomplished by forcing tp clr high, which if used to control the inhibit pin of the dc regulator (see figure 20 on page 25 ) will also switch off v out , depriving the external sram of power to the v cc pin. v out will automatically be disconnect ed from the battery if the tamper occurs during battery back-up (see figure 19 on page 24 ). by inhibiting the dc regulator, the user will also prevent other inpu ts from sourcing current to the external sram, which would allow it to retain data otherwise. the user may optionally connect an inverting charge pump to the v cc pin of the external sram (see figure 20 on page 25 ). depending on the process technology used for the manufacturing of the external sram, clearing the memory may require varying durations of negative potential on the v cc pin. this device configuration will allow the user to program the time needed for their particular application. control bits clrpw0 and clrpw1 determine the duration tp clr will be enabled (see figure 19 on page 24 and table 5 on page 25 ). note: when using the inverting charge pump, the user must also provide isolation in the form of two additional small-si gnal power mosfets. these will isolate the v out pin from both the
m41st87y, M41ST87W operating modes doc id 9497 rev 8 23/52 negative voltage generated by the charge pump during a tamper condition, and from being pulled to ground by the output of the charge pump when it is in shut-down mode (shdn = logic low). the gates of both mosfets should be connected to tp clr as shown in figure 20 on page 25 . one n-channel enhancement mosfet should be placed between the output of the inverting charge pump and the v out of the m41st87. the other mosfet should be an enhancement mode p-channel, and placed between v out of the m41st87 and v cc of the external sram. when tp clr goes high after a tamper condition occurs, the n-channel mosfet will tu rn on and the p-channel will turn off. during normal operating conditions, tp clr will be low and the p-channel will be on, while the n-channel will be off. table 4. tamper detection current (normally closed - tcm x = '0') figure 17. tamper detect sampling options tds x tchi/tclo x tamper circuit mode current at 3.0 v (typ) (1)(2) 1. when calculating battery lifetime , this current should be added to i bat current listed in table 17 on page 44 . 2. per tamper detect input unit 0 0 continuous monitoring / 10 m pull-up/-down 0.3 a 0 1 continuous monitoring / 1 m pull-up/-down 3.0 a 1 0 sampling (1hz) / 10 m pull-up/-down 0.3 na 1 1 sampling (1hz) / 1 m pull-up/-down 3.0 na ai07819 tamper lo, normally open tamper hi, normally closed user configuration tds x = 0 tds x = 1 tds x = 0 tds x = 1 tamper hi, normally open tamper lo, normally closed continuous monitoring continuous monitoring continuous monitoring sampled monitoring continuous monitoring sampled monitoring v cc (v out ) v cc (v out ) v cc (v out ) tcm x , tpm x
operating modes m41st87y, M41ST87W 24/52 doc id 9497 rev 8 figure 18. tamper current options figure 19. tamper output timing (with clr1 ext or clr2 ext = '1') - available in sox28 (mx) package only 1. if connected to a negative charge pump dev ice, this pin must be isolated from the charge pump by using both n-channel and p-channel mosfets as illustrated in figure 20 on page 25 . 2. if the device is in battery back-up; not on v cc (see section 2.6.9: ram clear external (clr1 ext and clr2 ext ) - available in sox28 package only on page 22 ). v out is forced to gnd during a tamper event when on v cc . 3. if tie x = '1.' 4. if abe = '1' and device is in battery backup mode. ai07820 tamper lo, normally open tamper hi, normally closed user configuration user configuration user configuration tds x = 0 tds x = 1 tds x = 0 tds x = 1 tamper hi, normally open tamper lo, normally closed continuous monitoring continuous monitoring continuous monitoring sampled monitoring continuous monitoring sampled monitoring v cc (v out ) tp x (tp1, tp2) v cc (v out ) v cc (v out ) tcm x , tpm x tchi/tclo = 0 tchi/tclo = 1 tchi/tclo = 0 tchi/tclo = 1 tp clr v out (1) rst tamper event (tb bit set) high-z (2) t rec t clr t clrd ai07083 e con irq/out (3) high-z (4)
m41st87y, M41ST87W operating modes doc id 9497 rev 8 25/52 table 5. tamper detect timing figure 20. ram clear hardware hookup (sox28 mx package only) 1. most inverting charge pumps drive out to ground when device shut down is enabled (shdn = logic low). therefore, an n- channel enhancement mode mosfet should be us ed to isolate the out pin from the v out of the m41st87. 2. in order to avoid turning on an on- chip parasitic diode when driving v out negative, a p-channel enhancement mode mosfet should be used to isolate the v out pin from the negative voltage generated by the inverting charge pump. symbol parameter clrpw 1 clrpw 0 min typ max unit t clrd (1) 1. with input capacitance = 70 pf and resistance = 50 . tamper ram clear ext delay x x 1.0 (2) 2. if the of bit is set, t clrd (min) = 0.5 ms. 1.5 2.0 ms t clr tamper clear timing 00 1 s 01 4 s 10 8 s 11 16 s ai07804 v cc pfo 1 ex scl m41st87y/w wdi rstin1 rstin2 pfi 1 pfi 2 v ss v bat f 32k irq/out sqw/ft rst v out e con sda cap+ cap? inverting charge pump shdn out in tp1 in tp clr tp2 in pushbutton reset pfo 2 low-power sram v cc negative output (?1 x v in ) e to rst to led display (2) (1) to nmi to int to 32khz inhibit 5v regulator v cc v in
operating modes m41st87y, M41ST87W 26/52 doc id 9497 rev 8 2.7 tamper detection operation the tamper pins are triggered based on the state of an external switch. two switch mode options are available, normally open or normally closed, based on the setting of the tamper connect mode bit (tcm x ). if the selected switch mo de is normally open (tcm x = '1'), the tamper pin will be triggered by being connected to v ss (if the tpm x bit is set to '0') or to v cc (if the tpm x bit is set to '1'), through the closing of the external switch. when the external switch is closed, the tamper bit (tb x ) will be immediately set, allo wing the user to determine if the device has been physically tampered with. if the selected switch mode is normally closed (tcm x = '0'), the tamper pin will be triggered by being pulled to v ss or to v out (depending on the state of the tpm x bit), through an internal pull-up/pull-down resistor as a result of opening the external switch. when a tamper event occurs, the tamper bits (tb1 and/or tb2) will be immediately set if teb x = '1.' if the tamper interrupt enable bit (tie x ) is set to a '1,' the irq /out pin will also be activated. the irq /out output is cleared by a read of the flags register (as seen in figure 24 on page 34 ), a reset of the tie bit to '0,' or the rst output is asserted. note: in order to avoid an inad vertent activation of the irq /out pin due to a prior tamper event, the flag register (0fh) should be read prior to resetting the teb x bit. the tamper bits are ?read only? bits and are reset only by writing the tamper enable bit (teb x ) to '0.' thus, when servicing a tamper interrupt, the user should read the flags register to clear the irq pin, then clear the teb x bit to clear the tb x flag, followed by setting teb x to again enable the tamper circuit. the tamper detect function operates both under normal power, and in battery backup. even if the trigger event occurs during a power-down condition, the tamper flag bit(s) will be set correctly. 2.8 sampling as the switch mode normally closed (tcm x = '0') requires a greater amount of current to maintain constant monitoring, the m41st87y/w offers a programmable tamper detect sampling bit (tds x ) to reduce the current drawn on v cc or v bat (see figure 17 on page 23 ). when enabled, the sampling frequency is once per second (1hz), for a duration of approximately 1 ms. when teb x is disabled, no current will be drawn by the tamper detection circuit. after a tamper event has been detected, no addition al current will be drawn. note: the oscillator mu st be running for tamper detection to operate in the sampling mode. if the oscillator is stopped, the tam per detection circuit will revert to constant monitoring. note: sampling in the tamper high mode (tpm x = '1') may be bypassed while on v cc by connecting the tpx in pin to v cc through an external resist or. this will allow constant monitoring when v cc is ?on? and revert to sampling when in battery backup (see figure 14 on page 20 ).
m41st87y, M41ST87W operating modes doc id 9497 rev 8 27/52 2.9 internal tamper pull-up/down current depending on the capacitive and resistive loading of the tamper pin input (tp xin ), the user may require more or less current from the internal pull-up/down used when monitoring the normally closed switch mode. the state of the tamper current hi/tamper current low bit (tchi/tclo x ) determines the sizing of the internal pull-up/-down. tchi/tclo x = '1' uses a 1 m pull-up/-down resistor, while tchi/tclo x = '0' uses a 10 m pull-up/-down resistor (see figure 18 on page 24 ). 2.10 avoiding inadvertent tampers (normally closed configuration) in some applications it may be necessary to us e a low pass filter to reduce electrical noise on the tamper input pin when the tcm x bit = 0 (normally closed). th is is especially true if the tamper detect switch is located some distance (> 6?) from the tamper input pin. a low pass filter can prevent unwanted, higher frequency noise from inadvertently being detected as a tamper condition caused by the ?antenna-effect? (produced by a longer signal wire or mesh). this low pass filter can be constructed using a series resistor (r) in conjunction with a capacitor (c) on the tamper input pin. the cut-off frequency f c is determined according to the formula: figure 21. low-pass filter implementation for noise immunity table 6. calculated cut-off frequency for typical capacitance and resistance values r ( )c (f) f c 1/f c (s) 1000 1.00e-09 15.9 mhz 6.28 s 1000 1.00e-06 159.2 hz 6.28 ms 5000 1.00e-09 31.8 khz 31.4 s 5000 1.00e-06 31.8 hz 31.4 ms 10000 1.00e-09 15.9 khz 62.8 s 10000 1.00e-06 15.9 hz 62.8 ms f c 12pirc ??? () ? = tp in r c to tamper detect switch ai11185
operating modes m41st87y, M41ST87W 28/52 doc id 9497 rev 8 2.11 tamper event time-stamp regardless of which tamper occurs first, not on ly will the appropriate tamper bit be set, but the event will also be automatically time-stamped. this is accomplished by freezing the normal update of the clock registers (00h through 07h) immediately following a tamper event. thus, when tampering occurs, the user may first read the time registers to determine exactly when the tamper event occurred, then re-enable the clock update to the current time (and reset the tamper bit, tb x ) by resetting the tamper enable bit (teb x ). the time update will then resume and the clock can be read to determine the current time. both tamper enable bits (teb x ) must always be set to '0' in order to read the current time. in the event of multiple tampers, the time -stamp will reflect the initial tamper event. note: if the teb x bit is set, the tamper event time-stamp will ta ke precedence over the power down time-stamp (see section 3.0.1: power-down time-stamp on page 29 ) and the ht bit (halt update) will not be set during the power-dow n event. if both ar e needed, the power down time-stamp may be accomplished by writ ing the time into the general purpose ram memory space when pfo is asserted.
m41st87y, M41ST87W clock operation doc id 9497 rev 8 29/52 3 clock operation the eight byte clock register (see table 7 on page 30 ) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. note: a write to any clock register (addresses 0 to 7h) will result in th e tenths/hundredths of seconds being reset to ?00.? furthermore, the tenths/hundredths of seconds cannot be written to any value other than ?00.? bits d6 and d7 of clock register 03h (century/hours register) contain the century bit 0 (cb0) and century bit 1 (cb1). bits d0 through d2 of register 04h contain the day (day of week). registers 05h, 06h, and 07h contain the date (day of month), month, and years. the ninth clock register is the control register (this is described in the clock calibration section). bit d7 of register 01h contains the stop bi t (st). setting this bit to a '1' will cause the oscillator to stop. if the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. when reset to a '0' the oscillator restarts within one second (typical). note: a write to any location within the first eight bytes of the clock register (00h-07h), including the ofie bit, clrpw0 bit, clrpw1 bit, ths bit, an d so forth, will result in an update of the system clock and a reset of the divi der chain. this could result in a significant corruption of the curr ent time, especially if the ht bit (see section 3.0.1: power-down time- stamp ) has not been previously reset. these non-clock related bits should be written prior to setting the clock, and remain unchanged until such time as a new clock time is also written. the eight clock registers may be read one byte at a time, or in a sequential block. the control register (address lo cation 08h) may be accessed independently. t he m41st87 will periodically copy the time/date counters to the user registers thus updating them. this process is suspended when any of these 8 registers is being accessed. it is also suspended during backup mode. suspending the updates ensures that the clock data being read does not change during the read. 3.0.1 power-down time-stamp upon power-down following a power failure, the halt update bit (ht) will automatically be set to a '1.' this will prevent the clock from updati ng the user registers, a nd will allow the user to read the time of the power-down event. note: when the ht bit is set or a tamper event occurs, the tenths/hundredths of a second register (00h) will automatically be reset to a value of ?0 0.? all other date and time registers (01h - 07h) will retain the value last up dated prior to the po wer-down or tamper event. the internal clock remains accurate and no time is lost as a result of the zeroing of the tenth/hundredths of a second register. when updates are resumed (due to resetting the ht bit or teb bit), the correct time will be displayed. resetting the ht bit to a '0' will allow the clock to update the user registers with the current time. note: if the teb bit is set, the power down time-s tamp will be disabled, and the tamper event time- stamp will take precedence (see section 2.7: tamper detection operation on page 26 ).
clock operation m41st87y, M41ST87W 30/52 doc id 9497 rev 8 3.1 timekeeper ? registers the m41st87y/w offers 22 internal registers which contain clock, control, alarm, watchdog, flag, square wave, and tamper data. the 8 clock registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as biport ? timekeeper cells). the external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. the internal divider (or clock) chain will be reset upon the completion of a write to any clock address (00h to 07h). the system-to-user transfer of clock data will be halted whenever the address being accessed is a clock address (00h to 07h). th e updates will resume either due to a stop condition or when the pointer increments to a non-clock or ram address. timekeeper and alarm registers st ore data in bcd format. c ontrol, watchdog and square wave registers store data in binary format. table 7. timekeeper ? register map addr data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds 10s/100s seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h ofie 10 minutes minutes minutes 00-59 03h cb1 cb0 10 hours hours (24-hour format) century/ hours 0-1/ 00-23 04h tr ths clrpw1 clrpw0 32ke day of week day 01-7 05h pfod 0 10 date date: day of month date 01-31 06h 0 0 0 10m month month 01-12 07h 10 years year year 00-99 08h out ft s calibration control 09h wds bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 0ah afe sqwe abe al 10m alarm month al month 01-12 0bh rpt4 rpt5 ai 10 date alarm date al date 01-31 0ch rpt3 ht ai 10 hour alarm hour al hour 00-23 0dh rpt2 alarm 10 minutes alarm minutes al min 00-59 0eh rpt1 alarm 10 seconds alarm seconds al sec 00-59 0fh wdf af 0 bl 0 of tb1 tb2 flags 10h 0 0 0 0 0 0 0 0 reserved 11h 0 0 0 0 0 0 0 0 reserved 12h 0 0 0 0 0 0 0 0 reserved 13h rs3 rs2 rs1 rs0 sqwod 0 0 0 sqw 14h teb1 tie1 tcm1 tpm1 tds1 tchi/ tclo 1 clr1 ext clr1 tamper1 15h teb2 tie2 tcm2 tpm2 tds2 tchi/ tclo 2 clr2 ext clr2 tamper2 16h-1dh rom serial number 8-byte 1eh-1fh reserved 2-byte 20h-9fh 128 user bytes
m41st87y, M41ST87W clock operation doc id 9497 rev 8 31/52 3.2 calibrating the clock the m41st87y/w is driven by a quartz cont rolled oscillator with a nominal frequency of 32,768 hz. the devices are tested to not e xceed 35 ppm (parts per million) oscillator frequency error at 25 c, with 20 ppm crystals, which translates to about 1.53 minutes per month. even better accuracy can be achieved with higher accuracy crystals. when the calibration circuit is properly employed, accuracy can be improved to better than 2 ppm at 25 c. the oscillation rate of crystals changes with temperature (see figure 22 on page 33 ). therefore, the m41st87y/w design employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscilla tor divider circuit at th e divide by 256 stage, as shown in figure 23: calibration waveform on page 33 . the number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration bits occupy the five lower order bits (d4-d0) in the control register (08h). these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 1 28 or lengthened by 2 56 oscillator cycles. if a binary '1' is loaded into the register, only th e first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. keys: 0 = must be set to zero rb0-rb1 = watchdog resolution bits 32ke = 32 khz output enable bit rpt1-rpt5 = alarm repeat mode bits abe = alarm in battery backup mode enable bit rs0-rs3 = sqw frequency af = alarm flag (read only) s = sign bit afe = alarm flag enable bit sqwe = square wave enable bl = battery low flag (read only) sqwod = square wave open drain bit bmb0-bmb4 = watchdog multiplier bits st = stop bit cb0-cb1 = century bits tb (1 and 2) = tamper bits (read only) clr (1 and 2) = ram clear bits tchi/tclo (1 and 2) = tamper current hi/tamper current low bits clr (1 and 2) ext = ram clear external bits tcm (1 and 2) = tamper connect mode bits clrpw0 = ram clear pulse width 0 bit tds (1 and 2) = tamper detect sampling bits clrpw1 = ram clear pulse width 1 bit teb (1 and 2) = tamper enable bits ft = frequency test bit ths = threshold bit ht = halt update bit tie (1 and 2) = tamper interrupt enable bits of = oscillator fail bit tpm (1 and 2) = tamper polarity mode bits ofie = oscillator fail interrupt enable bit tr = t rec bit out = output level wds = watchdog steering bit pfod = power-fail output open drain bit wdf = watchdog flag (read only)
clock operation m41st87y, M41ST87W 32/52 doc id 9497 rev 8 therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 ac tual oscillator cycles, that is +4.068 or ?2.034 ppm of adjustment per calibration step in the calibration register. as suming that the oscillator is running at exactly 32,768 hz, each of the 31 increments in the calibration byte would represent +10.7 or ?5.35 seconds per month which corresponds to a total range of +5.5 or ?2.75 minutes per month. two methods are available for ascertaining how much calibration a given m41st87y/w may require. the first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. calibration values, including the number of seconds lost or gained in a given period, can be found in application note an934, ?timekeeper ? calibration.? this allows the designer to give the end user the ability to calibrate the clock as the environm ent requires, even if the final product is packaged in a non-user serviceable enclosure. the designer could provide a simple utility that accesses the calibration byte. the second approach is better suited to a manufacturing environment, and involves the use of the sqw/ft pin. the pin will toggle at 512 hz, when the stop bit (st) is '0,' the frequency test bit (ft) is '1,' and sqwe is '0.' any deviation from 512 hz indicates the degree and direction of oscilla tor frequency shift at the test temperature. for example, a reading of 512.010124 hz would indicate a +20 ppm oscillator frequency erro r, requiring a ?10 (xx001010) to be loaded into the ca libration byte for correction. note that setting or changing the calibration byte does not affect the frequency test output frequency. if the sqwod bit = '1,' the sqw/ft pin is an open drain output which requires a pull-up resistor to v cc for proper operation. a 500 to 10 k resistor is recommended in order to control the rise time. the ft bit is cleared on power-down.
m41st87y, M41ST87W clock operation doc id 9497 rev 8 33/52 figure 22. crystal accuracy across temperature figure 23. calibration waveform 3.3 setting alarm clock registers address locations 0ah-0eh contain the alarm settings. the alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. it can also be programmed to go off while the m41st87y/w is in the battery back-up to serve as a system wake-up call. bits rpt5?rpt1 put the alarm in the repeat mode of operation. table 8 on page 34 shows the possible configurations. codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. when the clock information matches the alarm clock settings based on the match criteria defined by rpt5?rpt1, the af (alarm flag) is set. if afe (alarm flag enable) is also set, the ai07888 ?160 0 10203040506070 frequency (ppm) temperature c 80 ?10 ?20 ?30 ?40 ?100 ?120 ?140 ?40 ?60 ?80 20 0 ?20 = ?0.036 ppm/ c 2 0.006 ppm/ c 2 k = k x (t ? t o ) 2 f t o = 25 c 5 c ai00594b normal positive calibration negative calibration
clock operation m41st87y, M41ST87W 34/52 doc id 9497 rev 8 alarm condition activates the irq /out pin as shown in figure 25 on page 35 . to disable the alarm, write '0' to the alarm date register and to rpt5?rpt1. if the address pointer is allowed to increment to the flag register address, an alarm condition will not cause the interrupt/flag to occur until the address poin ter is moved to a different address. it should also be noted that if the last address written is the ?alarm seconds,? the address pointer will increment to the flag address, causing th is situation to occur. thus the user should not leave the address pointer at 0fh if using the alarm interrupt function. this is easily handled by simply reading past the flags registers before teminating a read sequence. the irq /out output is cleared by a read to the flags register. a subsequent read of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' the irq /out pin can also be activated in the battery backup mode. the irq /out will go low if an alarm occurs and both abe (alarm in battery backup mo de enable) and afe are set. the abe and afe bits are re set during power-up, therefore an alarm generated during power-up will only set af. the user can read the flag register at system boot-up to determine if an alarm was generated while the m41st87y/w was in the deselect mode during power-up. figure 25 on page 35 illustrates the backup mode alarm timing. figure 24. alarm interrupt reset waveform table 8. alarm repeat modes rpt5 rpt4 rpt3 rpt2 rpt1 alarm setting 11111once per second 11110once per minute 11100once per hour 11000once per day 10000once per month 00000once per year ai07086 irq/out active flag 0fh 0eh 10h high-z address pointer
m41st87y, M41ST87W clock operation doc id 9497 rev 8 35/52 figure 25. backup mode alarm waveform 3.4 watchdog timer the watchdog timer can be used to detect an out-of-control microprocessor. the user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. bits bmb4-bmb0 store a binary multiplier and the two lower order bits rb1-rb0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. the amount of time-out is then determined to be the multiplication of the five- bit multiplier value with the resolution. (for example: writing 00001110 in the watchdog register = 3*1 or 3 seconds). note: the accuracy of the timer is within the selected resolution. if the processor does not reset the timer within the specified period, the m41st87y/w sets the wdf (watchdog flag) and generates either a watchdog interrupt or a microprocessor reset. the most significant bit of the watchdog register is the watchdog steering bit (wds). when set to a '0,' the watchd og will activate the irq /out pin when timed-out. when wds is set to a '1,' the watchdog will output a negative pulse on the rst pin for t rec . the watchdog register, ft, afe, abe and sqwe bits will reset to a '0' at the end of a watchdog time-out when the wds bit is set to a '1.' the watchdog timer can be reset by two methods: 1) a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (wdi) or 2) the microprocessor can perform a write of the watchdog register. the time-out period then starts over. note: the wdi pin should be tied to v ss if not used and is only available in the sox28 (mx) package. in order to perform a software reset of the watchdog timer, the original time-out period can be written into the watchdog register, effectively restarting the count-down cycle. ai07087 v cc irq/out v pfd abe, afe bits in interrupt register af bit in flags register high-z v so high-z t rec
clock operation m41st87y, M41ST87W 36/52 doc id 9497 rev 8 should the watchdog timer time-out, and the wds bit is programmed to output an interrupt, either a transition of the wdi pin, or a value of 00h needs to be written to the watchdog register in order to clear the irq /out pin. this will also disabl e the watchdog function until it is again programmed correctly. a read of the flags register will reset the watchdog flag (bit d7; register 0fh) but does not clear the irq /out pin. the watchdog function is automatically disabled upon power-up and the watchdog register is cleared. 3.5 square wave output the m41st87y/w offers the user a programmable square wave function which is output on the sqw/ft pin. rs3-rs0 bits located in 13h establish the square wave output frequency. these frequencies are listed in table 9 . once the selection of the sqw frequency has been completed, the sqw/ft pin can be turned on and off under software control with the square wave enable bit (sqwe) located in register 0ah. the sqw/ft output is programmable as an n-channel, open drain output driver, or a full- cmos output driver. by setting the square wave open drain bit (sqwod) to a '1,' the output will be configured as an open drain (with i ol as specified in table 17 on page 44 ). when sqwod is set to '0,' the output will be configur ed as full-cmos (sink and source current as specified in table 17 on page 44 ). note: when configured as open drain (sqwod = '1'), the sqw/ft pin requires an external pull- up resistor. table 9. square wave output frequency square wave bits square wave rs3 rs2 rs1 rs0 frequency units 0000none? 000132.768khz 00108.192khz 00114.096khz 01002.048khz 01011.024khz 0110512hz 0111256hz 1000128hz 100164hz 101032hz 101116hz 11008hz 11014hz 11102hz 11111hz
m41st87y, M41ST87W clock operation doc id 9497 rev 8 37/52 3.6 full-time 32 khz square wave output the m41st87y/w offers the user a special 32 khz square wave function which defaults to output on the f 32k pin (pin 21) as long as v cc v so , and the oscillator is running (st bit = '0'). this function is available within one second (typ) of initial power-up and can only be disabled by setting the 32 ke bit to '0' or the st bit to '1.' if not used, the f 32k pin should be disconnected and allowed to float. note: the f 32k pin is an open drain which requires an external pull-up resistor. 3.7 power-on reset the m41st87y/w continuously monitors v cc . when v cc falls to the power fail detect trip point, the rst pulls low (open drain) and remains low on power-up for t rec after v cc passes v pfd (max). the rst pin is an open drain output and an appropriate pull-up resistor should be chosen to control rise time. note: a power-on reset will result in resetting the followin g control bits to '0': ofie, afe, abe, sqwe, ft, wds, bmb0-bmb4, rb0, rb1, tie1, and tie2 (see table 13 on page 41 ). 3.8 reset inputs (rstin1 & rstin2 ) the m41st87y/w provides two independent inputs which can generate an output reset. the function of these resets is identical to a reset generated by a power cycle. table 10 and figure 26 illustrate the ac reset characteristics of this function. pulses shorter than t r1 and t r2 will not generate a reset condition. rstin1 and rstin2 are each internally pulled up to v cc through a 100 k resistor. note that rstin1 triggers on the falling edge while rstin2 triggers on the rising edge. note: rstin2 is available only in the sox28 (mx) package. figure 26. rstin1 & rstin2 timing waveforms ai07072 rstin1 rst rstin2 t r1 t rec hi-z t r2 t rec hi-z
clock operation m41st87y, M41ST87W 38/52 doc id 9497 rev 8 table 10. reset ac characteristics 3.9 power-fail comparators (1 and 2) two power-fail inputs (pfi 1 and pfi 2 ) are compared to an internal reference voltage (1.25v). if either pfi 1 or pfi 2 is less than the power-fail threshold (v pfi ), the associated power-fail output (pfo 1 or pfo 2 ) will go low. this function is in tended for use as an under-voltage detector to signal a failing power supply. typically pfi 1 and pfi 2 are connected through external voltage dividers (see figure 5 on page 11 ) to either the unregulated dc input (if it is available) or the regulated output of the v cc regulator. the voltage divider can be set up such that the voltage at pfi 1 or pfi 2 falls below v pfi several milliseconds before the regulated v cc input to the m41st87y/w or the microprocessor drops below the minimum operating voltage, thus providing an early warning of power failure. during battery back-up, the power-fail comparator turns off and pfo 1 and pfo 2 go (or remain) low. this occurs after v cc drops below v pfd (min). when power returns, pfo 1 and pfo 2 are forced high, irrespective of v pfi for the write protect time (t rec ), which is the time from v pfd (max) until the inputs are recognized. at the end of this time, the power-fail comparator is enabled and pfo 1 and pfo 2 follow pfi 1 and pfi 2 . if the comparator is unused, pfi 1 or pfi 2 should be connected to v ss and the associated pfo 1 or pfo 2 left unconnected. 3.10 power-fail outputs the pfo 1 and pfo 2 outputs are programmable as n-channel, open drain output drivers, or full-cmos output drivers. by setting the power-fail output open drain bit (pfod) to a '1,' the output will be configured as open drain (with i ol as specified in table 17 on page 44 ). when pfod is set to '0,' the outputs will be configur ed as full-cmos (sink and source current as specified in table 17 on page 23 ). note: when configured as open drain (pfod = '1'), pfo 1 and pfo 2 will require an external pull- up resistor. symbol parameter (1) 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 4.5 to 5.5 v or 2.7 to 3.6 v (except where noted). min max unit t r1 (2) 2. pulse widths of less than 100 ns will result in no reset (for noise immunity). rstin1 low to rst low (min pulse width) 100 200 ns t r2 (2) rstin2 low to rstin2 high (min pulse width) 100 200 ns t rec (3) 3. programmable (see table 12 on page 40 ). same function as power-on reset. rstin1 or rstin2 high to rst high 96 98 (3) ms
m41st87y, M41ST87W clock operation doc id 9497 rev 8 39/52 3.11 century bits these two bits will increment in a binary fashion at the turn of the century, and handle leap years correctly. refer to table 11 . these bits represent the next higher order bits of the years register (07h), and should be set accordingly. for example, for the year 2100, they would be set to 1 (d7 = 0 and d6 = 1), and for the year 2300, they would be set to 3 (d7 = 1 and d6 = 1). once set, they will increment every 100 years. provided they are set as described above, the da te register (05h) will properly manag e leap day at the turn of any century. leap day does not occur in turn-of-century years except for those which are multiples of 400. thus, with cb1 and cb0 proper ly set, the device will omit leap day from the appropriate turn-of-century years. table 11. century bits examples 3.12 output driver pin when the tie bit, ofie bit, afe bit, and watchdog register are not set to generate an interrupt, the irq /out pin becomes an output driver that reflects the contents of d7 of the control register. in other words, when d7 (out bit) is a '0,' then the irq /out pin will be driven low. with the abe bit set to '1,' the out pin will continue to be driven low in battery backup. note: the irq /out pin is an open drain which requ ires an external pull-up resistor. 3.13 battery low warning the m41st87y/w automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. the battery low (bl) bit, bit d4 of flags register 0fh, will be set if the battery voltage is found to be less than approximately 2.5 v. the bl bit will remain set until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. if a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to maintain data integrity in the sram. data should be considered suspect and verified as correct. a fresh battery should be installed. if a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. however, data is not compromised due to the fact that a nominal v cc is supplied. in order to ensure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. the battery should be replaced while v cc is applied to the device. cb1 cb0 leap year? example (1) 1. leap year occurs every four years (f or years evenly divisible by four), except for y ears evenly divisible by 100. the only exceptions are those years evenly divisible by 400 (the y ear 2000 was a leap year, year 2100 is not). 0 0 yes 2000 0 1 no 2100 1 0 no 2200 1 1 no 2300
clock operation m41st87y, M41ST87W 40/52 doc id 9497 rev 8 the m41st87y/w only monitors the battery when a nominal v cc is applied to the device. thus applications which require extensive dura tions in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. 3.14 t rec bit bit d7 of clock register 04h contains the t rec bit (tr). t rec refers to the automatic continuation of the deselect time after v cc reaches v pfd . this allows for a voltage settling time before writes may again be performed to the device after a power-down condition. the t rec bit will allow the user to set the length of this deselect time as defined by table 12 . table 12. t rec definitions 3.15 electronic serial number the m41st87y/w has a unique 8-byte lasered serial number with parity. this serial number is ?read only? and is generated such that no two devices will contain an identical number. 3.16 oscillator stop detection if the oscillator fail (of) bit is internally set to a '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time, and can be used to judge the validity of the clock and date data. this bit will be set to '1' any time the oscillator stops. the following conditions can cause the of bit to be set: the first time power is applied (defaults to a '1' on power-up). the voltage present on v cc or battery is insufficie nt to support oscillation. the st bit is set to '1.' if the oscillator fail interrupt enable bi t (ofie) is set to a '1,' the irq /out pin will also be asserted. the irq /out output is cleared by resetting the of bit to '0,' resetting the ofie bit to '0,' or if the rst output is asserted (but is not cleared by reading the flag register). the of bit will remain set to '1' until written to logic '0.' the oscillator must start and have run for at least 4 seconds before attempting to reset the of bit to '0.' this function operates both under normal power and in battery backup. if the trigger event occurs during a power- down condition, this bit will be set correctly. note: the abe bit must be set to '1' for the irq /out pin to be activa ted in battery backup. t rec bit (tr) stop bit (st) t rec time units min max 0 0 96 98 (1) 1. default setting. ms 0140200ms 1 x 50 2000 s
m41st87y, M41ST87W clock operation doc id 9497 rev 8 41/52 3.17 initial power-on defaults note: all other control bits are undetermined. table 13. default values condition tr st of ofie ht (1) out ft afe initial power-up 0 0 1 0 1 1 0 0 subsequent power-up (with battery backup) (2)(3) uc uc uc 0 ? 1 ? uc 0 ? 0 ? condition abe sqwe sqwod pfod watchdog register (4) initial power-up 0 0 1 1 0 subsequent power-up (with battery backup) (2)(3) 0 ? 0 ? uc uc 0 ? condition 32ke ths teb1 and 2 tcm 1 and 2 tpm1 and 2 tds1 and 2 initial power-up 1 (5) 00 0 0 0 subsequent power-up (with battery backup) (2) uc uc uc uc uc uc condition tchi/tclo 1 and 2 clr1 and 2 tie1 and 2 clrpw0 clrpw1 clr1 ext and clr2 ext initial power-up 0 0 0 0 0 0 subsequent power-up (with battery backup) (2) uc uc 0 ? uc uc uc 1. when teb x is set to '1,' the ht bit will not be set on pow er-down (tamper time-stamp will have precedence). 2. uc = unchanged. 3. ? = v cc rising; ? = v cc falling. 4. wds, bmb0-bmb4, rb0, rb1. 5. 32 khz output valid only on v cc .
maximum ratings m41st87y, M41ST87W 42/52 doc id 9497 rev 8 4 maximum ratings stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 14. absolute maximum ratings caution: negative undershoots below ?0.3 v are not allowed on any pin while in the battery backup mode. symbol parameter value unit t stg storage temperature (v cc off, oscillator off) ?55 to 125 c t sld lead solder temperature for 10 seconds ssop20 (ss) 260 (1) 1. reflow at peak temperature of 260 c. the time above 255 c must not exceed 30 seconds. c sox28 (mx) 240 (2) 2. reflow at peak temperature of 240 c. the time above 235c must not exceed 20 seconds. c v io input or output voltage ?0.3 to v cc +0.3 v v cc supply voltage m41st87y ?0.3 to 7.0 v M41ST87W ?0.3 to 4.6 v i o output current 20 ma p d power dissipation 1 w ja thermal resistance, junction to ambient ssop20 (ss) 83.0 c/w sox28 (mx) c/w
m41st87y, M41ST87W dc and ac parameters doc id 9497 rev 8 43/52 5 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. table 15. dc and ac measurement conditions note: output high z is defined as the point where data is no longer driven. figure 27. ac testing input/output waveforms table 16. capacitance parameter m41st87y M41ST87W v cc supply voltage 4.5 to 5.5 v 2.7 to 3.6 v ambient operating temperature ?40 to 85 c ?40 to 85 c load capacitance (c l ) 100 pf 50 pf input rise and fall times 50 ns 50 ns input pulse voltages 0.2 to 0.8v cc 0.2 to 0.8v cc input and output timing ref. voltages 0.3 to 0.7v cc 0.3 to 0.7v cc symbol parameter (1)(2) 1. effective capacitance measured with power supply at 5 v. sampled only, not 100% tested. 2. at 25 c, f = 1 mhz. min max unit c in input capacitance 7 pf c out (3) 3. outputs are deselected. output capacitance 10 pf t lp low-pass filter input time constant (sda and scl) 50 ns ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc
dc and ac parameters m41st87y, M41ST87W 44/52 doc id 9497 rev 8 table 17. dc characteristics sym parameter test condition (1) m41st87y M41ST87W unit min typ max min typ max i bat (2) battery current osc on t a = 25 c, v cc = 0 v, v bat = 3 v 500 700 500 700 na battery current osc off 50 50 na i cc1 supply current f = 400 khz 1.4 0.75 ma i cc2 supply current (standby) scl, sda v cc ? 0.3 v 1 0.50 ma i li (3) input leakage current 0v v in v cc 1 1 a input leakage current (pfi) ?25 2 25 ?25 2 25 na i lo (4) output leakage current 0v v in v cc 1 1 a i out1 (5) v out current (active) v out1 > v cc ? 0.3 v 175 100 ma i out2 v out current (battery backup) v out2 > v bat ? 0.3 v 100 100 a v ih input high voltage 0.7v cc v cc + 0.3 0.7v cc v cc + 0.3 v v il input low voltage ?0.3 0.3v cc ?0.3 0.3v cc v v bat battery voltage 2.5 3.0 v cc 2.5 3.0 v cc v v oh (6) output high voltage i oh = ?1.0 ma 2.4 2.4 v pull-up supply voltage (open drain) irq /out, rst , f 32k 5.5 3.6 v v ohb (7) v oh (battery backup) i out2 = ?1.0 a (8) 2.9 2.9 v v ol output low voltage i ol = 3.0 ma 0.4 0.4 v output low voltage (open drain) (9) i ol = 10 ma 0.4 0.4 v v pfd power fail deselect ths bit = 0 4.20 4.35 4.50 2.55 2.62 2.70 v ths bit = 1 4.50 4.60 4.75 2.80 2.88 3.00 v v pfi1, v pfi2 pfi input threshold v cc = 5 v (y) 1.225 1.250 1.275 v v cc = 3 v (w) 1.225 1.250 1.275 v pfi hysteresis pfi rising 20 70 20 70 mv
m41st87y, M41ST87W dc and ac parameters doc id 9497 rev 8 45/52 v so battery backup switchover 2.5 2.5 v r sw external switch resistance on tamper pin 500 500 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 4.5 to 5.5 v or 2.7 to 3.6 v (except where noted). 2. measured with v out and e con open. not including tamper detection current (see table 4 on page 23 ). 3. rstin1 and rstin2 internally pulled-up to v cc through 100 k resistor. wdi internally pulled-down to v ss through 100 k resistor. 4. outputs deselected. 5. external sram must match rtc supervisor chip v cc specification. 6. for pfo 1 and pfo 2 (if pfod = '0'), sqw/ft (if sqwod = '0'), and tp clr pins (cmos). 7. conditioned output (e con ) can only sustain cmos leakage current in t he battery backup mode. higher leakage currents will reduce battery life. 8. tp clr output can source ?300 a (typ) for v bat = 2.9 v. 9. for irq /out, sqw/ft (if sqwod = '1'), pfo 1 and pfo 2 (if pfod = '1'), rst , sda, and f 32k pins (open drain). table 17. dc characteristics (continued) table 18. crystal (1) electrical characteristics symbol parameter (2) min typ max units f o resonant frequency 32.768 khz r s series resistance 65 (3) k c l load capacitance 12.5 pf 1. user supplied for the 20-lead ssop package. stmicroelectronics recommends the kds dt-38 (3 x 8 mm) for thru-hole, or the kds dmx-26s (3.2 x 8 mm) for surface-mount, tuning fo rk-type quartz crystals. fo r contact information, see section 8: references on page 50 . 2. load capacitors are integrated within the m41st87. circuit board layout considerations for the 32.768 khz crystal of minimum trace lengths and isolation from rf generating signals should be taken into account. 3. t a = ?40 to 85 c (guaranteed by design).
dc and ac parameters m41st87y, M41ST87W 46/52 doc id 9497 rev 8 figure 28. power down/up mode ac waveforms 1. e con available in the sox28 (mx) package only. table 19. power down/up ac characteristics symbol parameter (1) 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 4.5 to 5.5 v or 2.7 to 3.6 v (except where noted). min typ max unit t f (2) 2. v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/writ e protection not occurring until 200 s after v cc passes v pfd (min). v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. v pfd (min) to v ss v cc fall time 10 s t pd ex at v ih before power down 0 s t pfd pfi to pfo propagation delay 15 25 s t r v pfd (min) to v pfd (max) v cc rise time 10 s t rb v ss to v pfd (min) v cc rise time 1 s t rec power-up deselect time 96 98 (4) 4. programmable (see table 12 on page 40 ) ms ai07085 v cc inputs (per control input) outputs don't care high-z t f t fb t r t pd t rb valid valid (per control input) recognized recognized v pfd (max) v pfd (min) v so t rec rst e con (1) pfo valid valid
m41st87y, M41ST87W package mechanical data doc id 9497 rev 8 47/52 6 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 29. sox28 ? 28-lead plastic small outline, 300 mils, embedded crystal outline note: drawing is not to scale. e 14 e d c h 15 28 1 b so-e a1 l a1 h x 45 a a2 ddd table 20. sox28 ? 28-lead plastic small outline, 300 mils, embedded crystal mechanical data symbol millimeters inches typ min max typ min max a 2.44 2.69 0.096 0.106 a1 0.15 0.31 0.006 0.012 a2 2.29 2.39 0.090 0.094 b 0.41 0.51 0.016 0.020 c 0.20 0.31 0.008 0.012 d 17.91 18.01 0.705 0.709 ddd 0.10 0.004 e 7.57 7.67 0.298 0.302 e1.27? ?0.050? ? h 10.16 10.52 0.400 0.414 l 0.51 0.81 0.020 0.032 a 08 08 n28 28
package mechanical data m41st87y, M41ST87W 48/52 doc id 9497 rev 8 figure 30. ssop20 ? 20-lead, shrink, small outline package outline table 21. ssop20 ? 20-lead, shrink, small outline package mechanical data sym mm in min typ max min typ max a 2.000 0.079 a1 0.050 0.002 a2 1.650 1.750 1.850 0.065 0.069 0.073 b 0.220 0.380 0.009 0.015 c 0.090 0.250 0.004 0.010 d 6.900 7.200 7.500 0.272 0.283 0.295 e 7.400 7.800 8.200 0.291 0.307 0.323 e1 5.000 5.300 5.600 0.197 0.209 0.220 e 0.650 0.026 l 0.550 0.750 0.950 0.022 0.030 0.037 l1 1.250 0.049 k0d 4d 8d0d4d8d ddd 0.100 0.004 0061436_c
m41st87y, M41ST87W part numbering doc id 9497 rev 8 49/52 7 part numbering table 22. ordering information scheme for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: m41st 87y mx 6 device type m41st supply voltage and write protect voltage 87y = v cc = 4.75 to 5.5 v ths bit = '1': 4.50 v v pfd 4.75 v v cc = 4.5 to 5.5 v ths bit = '0': 4.20 v v pfd 4.50 v 87w = v cc = 3.0 to 3.6 v; ths bit = '1': 2.80 v v pfd 3.00 v v cc = 2.7 to 3.6 v; ths bit = '0': 2.55 v v pfd 2.70 v package mx (1)(2) = sox28 1. the sox28 package includes an embedded 32,768 hz crystal. 2. lead-free second level interconnect and rohs compliant (by exemption). ss (3) = ssop20 3. available in 3.3 v (w) version only. temperature range 6 = ?40 to 85 c shipping method blank = ecopack ? package, tubes f = ecopack ? package, tape & reel (4) 4. ssop20 (ss) package only.
references m41st87y, M41ST87W 50/52 doc id 9497 rev 8 8 references kds, the crystal component supplier mentioned in this document, can be contacted at kouhou@kdsj.co.jp or http://www.kds.info/index_en.htm
m41st87y, M41ST87W revision history doc id 9497 rev 8 51/52 9 revision history table 23. document revision history date revision changes may-2002 1 first issue. 23-apr-2003 2 document promoted to preliminary data. 10-jul-2003 2.1 update tamper information ( figure 4 , 5 , 14 , 15 , 16 ; table 17 , 4 , 12 ). 11-sep-2003 2.2 update electrical, charge pump, and clock information ( table 17 ; figure 5 , 19 , 20 ). 15-jun-2004 3 reformatted; added lead-free info rmation; updated characteristics ( figure 2 ; table 1 , 14 , 17 , 22 ). 7-sep-2004 4 update maximum ratings ( table 14 ). 29-jun-2005 5 clarify nc connections, add inadvert ent tamper, update mx attribute ( figure 2 , 21 ; table 1 , 6 , 22 ). 28-mar-2006 6 update to ?avoiding inadvertent tamper paragraph? paragraph. 10-sep-2008 7 reformatted document and title change; updated cover page, figure 4 , 15 , 20 , section 6: package mechanical data . 31-mar-2010 8 added ssop 20-pin package (updated cover page, section 1.1 , figure 1 , 4 , 5 , 13 , 28 , table 1 , 2 , section 3.4 , section 3.8 , added figure 3 , 30 , ta ble 18 , 21 , section 8 ); updated ta ble 11 , 14 , 17 , 18 , 22 , figure 10 , 11 , figure 15.16 , 19 , 24 , 27 , 28 , text in section 1 , section 2 , section 2.1 , section 2.1.5 , section 2.4 , section 2.5 , section 2.6.1 , section 2.6.3 , section 2.6.5 , section 2.6.6 , section 2.6.8 , section 2.6.9 , section 2.7 , section 2.8 , section 3 , section 3.0.1 , section 3.1 , section 3.2 , section 3.3 , section 3.4 , section 3.8 , section 3.9 , section 3.11 , section 3.13 , section 3.16 , section 3.17 , section 6 ; reformatted document.
m41st87y, M41ST87W 52/52 doc id 9497 rev 8 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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